Constant ON time control in a direct current-to-direct current (DC/DC) buck converter is well-suited for a single channel converter. This control architecture often utilizes the valley of a ripple voltage of an output filter capacitor to initiate a new pulse width modulated (PWM) pulse and does not use a fixed oscillator clock to initiate this pulse. In lieu of the output filter capacitor ripple, an emulated ripple can be used for the valley control. The emulated ripple is synchronized to the PWM pulse, meaning a TON timer ends a PWM pulse and also turns off the ripple ramp. Similarly, when the valley of the ramp crosses a reference voltage, a new PWM pulse starts.
In an analog-controlled switching power supply, accurate output voltage sensing is often necessary or desirable to maintain regulation. The output voltage of the switching power supply can include a DC average value plus some amount of AC ripple. The output voltage of the power supply is typically to be regulated at this average value.
It is sometimes desirable to, as a way of determining the “next pulse,” use a triangular waveform that is compared to a control signal. This triangular waveform may be generated using a variety of methods, each method with trade-offs in performance. For example, a fixed triangular waveform in a Voltage Mode Converter provides ease of use but has variable gain with a change in input voltage.
One way to generate a triangular control waveform is to use current sources to charge and discharge a capacitor. Balancing the charge and discharge rates is typically critical in order to achieve stable control. Assume the current sources are used to charge and discharge the capacitor in a periodic fashion to generate the triangular waveform. In this case, it is likely that tolerances of the current sources and/or the timing of the turn-on or turn-off of the current sources will cause an ampere-second imbalance between the charge and discharge intervals. This results in a buildup of DC bias voltage across the capacitor. If left uncorrected, the DC bias builds to a level such that the voltage on the capacitor is no longer a periodic signal but rather becomes saturated either at the supply voltage rail or at ground.
For ramp generation, other solutions may use switches to connect and disconnect one or more resistors to and from a capacitor. This approach is limited in dynamic operating range and is susceptible to noise.
Other solutions may use current sources but require manual adjustment of the current sources or timing circuits or the addition of a resistor to “bleed” excess current from one side of the capacitor in order to maintain a zero DC bias condition. These solutions generally also have limited dynamic range.
In output ripple-controlled converters (such as Hysteretic, Constant ON time, Constant OFF time, and some fixed frequency “output ripple controlled” converters), the “decision point” for regulation (i.e. to trigger the next ON or OFF pulse to maintain the correct average energy at the converter output) is made at the peak or valley of the output voltage ripple waveform. By triggering at a peak or valley of the output voltage ripple, a “peak-to-average” error develops. In some cases, such as during a load transient, this error can cause a peak of the output voltage to exceed voltage (deviation from nominal) specifications.
In those applications where a Dual Differential Difference Amplifier (3DA) configuration is used, particularly in peak or valley detection ripple converters, current approaches typically use an external circuit to offset either the reference or sensed output voltage. This is done to level-shift the converter output voltage in order to meet a desired average value.